NXP Semiconductors /MIMXRT1052 /USDHC1 /INT_SIGNAL_EN

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Interpret as INT_SIGNAL_EN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CCIEN_0)CCIEN 0 (TCIEN_0)TCIEN 0 (BGEIEN_0)BGEIEN 0 (DINTIEN_0)DINTIEN 0 (BWRIEN_0)BWRIEN 0 (BRRIEN_0)BRRIEN 0 (CINSIEN_0)CINSIEN 0 (CRMIEN_0)CRMIEN 0 (CINTIEN_0)CINTIEN 0 (RTEIEN_0)RTEIEN 0 (TPIEN_0)TPIEN 0 (CTOEIEN_0)CTOEIEN 0 (CCEIEN_0)CCEIEN 0 (CEBEIEN_0)CEBEIEN 0 (CIEIEN_0)CIEIEN 0 (DTOEIEN_0)DTOEIEN 0 (DCEIEN_0)DCEIEN 0 (DEBEIEN_0)DEBEIEN 0 (AC12EIEN_0)AC12EIEN 0 (TNEIEN_0)TNEIEN 0 (DMAEIEN_0)DMAEIEN

CIEIEN=CIEIEN_0, BWRIEN=BWRIEN_0, DMAEIEN=DMAEIEN_0, BGEIEN=BGEIEN_0, CCIEN=CCIEN_0, RTEIEN=RTEIEN_0, TNEIEN=TNEIEN_0, CTOEIEN=CTOEIEN_0, DEBEIEN=DEBEIEN_0, TPIEN=TPIEN_0, CCEIEN=CCEIEN_0, BRRIEN=BRRIEN_0, DINTIEN=DINTIEN_0, CINTIEN=CINTIEN_0, CINSIEN=CINSIEN_0, AC12EIEN=AC12EIEN_0, DTOEIEN=DTOEIEN_0, CEBEIEN=CEBEIEN_0, TCIEN=TCIEN_0, DCEIEN=DCEIEN_0, CRMIEN=CRMIEN_0

Description

Interrupt Signal Enable

Fields

CCIEN

Command Complete Interrupt Enable

0 (CCIEN_0): Masked

1 (CCIEN_1): Enabled

TCIEN

Transfer Complete Interrupt Enable

0 (TCIEN_0): Masked

1 (TCIEN_1): Enabled

BGEIEN

Block Gap Event Interrupt Enable

0 (BGEIEN_0): Masked

1 (BGEIEN_1): Enabled

DINTIEN

DMA Interrupt Enable

0 (DINTIEN_0): Masked

1 (DINTIEN_1): Enabled

BWRIEN

Buffer Write Ready Interrupt Enable

0 (BWRIEN_0): Masked

1 (BWRIEN_1): Enabled

BRRIEN

Buffer Read Ready Interrupt Enable

0 (BRRIEN_0): Masked

1 (BRRIEN_1): Enabled

CINSIEN

Card Insertion Interrupt Enable

0 (CINSIEN_0): Masked

1 (CINSIEN_1): Enabled

CRMIEN

Card Removal Interrupt Enable

0 (CRMIEN_0): Masked

1 (CRMIEN_1): Enabled

CINTIEN

Card Interrupt Interrupt Enable

0 (CINTIEN_0): Masked

1 (CINTIEN_1): Enabled

RTEIEN

Re-Tuning Event Interrupt Enable

0 (RTEIEN_0): Masked

1 (RTEIEN_1): Enabled

TPIEN

Tuning Pass Interrupt Enable

0 (TPIEN_0): Masked

1 (TPIEN_1): Enabled

CTOEIEN

Command Timeout Error Interrupt Enable

0 (CTOEIEN_0): Masked

1 (CTOEIEN_1): Enabled

CCEIEN

Command CRC Error Interrupt Enable

0 (CCEIEN_0): Masked

1 (CCEIEN_1): Enabled

CEBEIEN

Command End Bit Error Interrupt Enable

0 (CEBEIEN_0): Masked

1 (CEBEIEN_1): Enabled

CIEIEN

Command Index Error Interrupt Enable

0 (CIEIEN_0): Masked

1 (CIEIEN_1): Enabled

DTOEIEN

Data Timeout Error Interrupt Enable

0 (DTOEIEN_0): Masked

1 (DTOEIEN_1): Enabled

DCEIEN

Data CRC Error Interrupt Enable

0 (DCEIEN_0): Masked

1 (DCEIEN_1): Enabled

DEBEIEN

Data End Bit Error Interrupt Enable

0 (DEBEIEN_0): Masked

1 (DEBEIEN_1): Enabled

AC12EIEN

Auto CMD12 Error Interrupt Enable

0 (AC12EIEN_0): Masked

1 (AC12EIEN_1): Enabled

TNEIEN

Tuning Error Interrupt Enable

0 (TNEIEN_0): Masked

1 (TNEIEN_1): Enabled

DMAEIEN

DMA Error Interrupt Enable

0 (DMAEIEN_0): Masked

1 (DMAEIEN_1): Enable

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